Senior ASIC Verification Engineer
Core
Senior ASIC Verification Engineer responsible for RTL SoC/Subsystem verification of ARM-based Smart Edge SoCs using industry-standard methodologies.
Role type
Senior IC ASIC Verification Engineer
Builds
Smart Edge SoCs for network/systems control, management security systems, and IIoT
Domain
Semiconductor / Hardware Security / AI Infrastructure
Deliverable
production ML models | product features
Required skills
UVM environment development, test plan definition, C/Assembly/System Verilog, RTL and gate-level simulation, coverage analysis, AMBA AXI/AHB/APB protocols, interface protocol verification (PCIe, USB, Ethernet, DDR, I2C, SPI, etc.), post-silicon bring-up/debug, scripting (Perl/Python/Shell), repository management (Bitbucket/Jenkins), bug tracking (JIRA)
Preferred skills
None stated
Technologies
UVM, Portable Stimulus, Formal verification, System Verilog, C, Assembly, Perl, Python, Shell, Bitbucket, Jenkins, JIRA, AMBA AXI, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C, I3C, SPI, SD/SDIO/eMMC, UART
Responsibilities
Develop test plan definitions, perform micro-architecture design verification, execute top-level and block-level functional/performance verification, support test program development, collaborate with firmware/software/DV/FPGA/DFT/SoC integration/backend teams
Seniority
Senior, hands-on IC
