Sr Principal Engineer, Chip Lead
Core
Leading RTL design for power-efficient SoCs, driving integration across architecture, verification, and physical design teams to deliver semiconductor solutions.
Role type
Sr Principal Engineer, Chip Lead (RTL Design)
Builds
Power-efficient System-on-Chip (SoC) solutions for automotive, industrial, infrastructure, and IoT markets.
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/SystemVerilog), CPU-based chip design, D2D protocols (UCIe/Bunch-of-wires), Microcontroller/Microprocessor design, Timing closure, PPA optimization, Low-power design, Multi-clock domain architectures, Synthesis/STA, Memory controllers (DDR/LPDDR/Flash), IP selection.
Preferred skills
High Speed Peripherals (DDR, PCIe, Ethernet, GPU, VPU), NIC/FlexNOC interconnect, Flash memory subsystems.
Technologies
Verilog, SystemVerilog, UCIe, AHB, AXI, CHI, ROM, RAM, Flash, LPDDR, DDR3, DDR4, PCIe, Ethernet, GPU, VPU, FlexNOC
Responsibilities
Drive chip integration and team alignment to meet project goals; Create RTL micro-arch specifications and drive RTL design; Optimize RTL for timing, power, and area targets; Collaborate with verification, firmware, and physical design teams; Provide technical leadership to junior engineers; Support post-silicon debug; Make IP selection and make/buy decisions.
Seniority
Sr Principal, hands-on IC with technical leadership
