Senior Silicon Validation Engineer
Core
Lead validation and characterisation of analogue and mixed-signal ASICs for trapped-ion quantum processors, from test planning through first-silicon bring-up, debug, and system integration at cryogenic temperatures.
Role type
Senior IC silicon validation engineer (cryo-CMOS)
Builds
Reusable hardware validation platforms, software automation, and test suites for quantum processor chips
Domain
Quantum computing hardware / Cryo-CMOS / Mixed-signal ASICs
Required skills
Analogue/mixed-signal silicon validation, cryogenic measurement, Python automation, PCB design/debugging, signal integrity analysis, test strategy definition, technical mentoring
Preferred skills
Cryogenic testing, bare-die probing, FPGA development, circuit simulation, C/C++
Technologies
Python, Git, Oscilloscopes, Precision sources/meters, Signal generators, Spectrum/logic analysers, SPI/I2C/JTAG interfaces
Responsibilities
Own silicon validation strategy and acceptance criteria; Lead first-silicon bring-up and characterisation of analog/digital blocks; Develop validation boards, fixtures, and automated test suites; Plan and lead cryogenic measurements and failure analysis; Mentor engineers and document test methods
Seniority
Senior, hands-on IC with leadership responsibilities
