Senior QPU Design Engineer
Core
Design and layout of ion trap chips for high-performance quantum processing units (QPU), integrating photonics and CMOS interfaces.
Role type
Senior IC layout engineer (quantum photonics)
Builds
Ion trap chips for utility-scale quantum computers
Domain
Quantum computing hardware / Photonics / Semiconductor manufacturing
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Chip layout, multi-layer routing, photonics design, ion trap design, IC packaging, GDSFactory (Python), Cadence
Preferred skills
Scripted layout generation, cross-functional collaboration, project ownership
Technologies
GDSFactory, Python, Cadence
Responsibilities
Translate operational requirements into chip layout; guide chips through design process from requirements to tape-out; collaborate with scientists to settle specifications; coordinate with teams for feasibility and compatibility; own delivery of final tape-out.
Seniority
Senior, hands-on IC
