Master Thesis: Requirements to Verified RTL Releases: A Multi-Agent Traceability Framework for ASIC
Core
Develop and test a multi-agent ecosystem for feature-centric traceability and quality assurance in ASIC IP development, connecting requirements with Jira work items, RTL revisions, and verification evidence.
Role type
Master Thesis Researcher (ASIC IP & Traceability)
Builds
An auditable artifact graph, change-impact analysis, and explainable quality-marker reports for ASIC IP releases.
Domain
Semiconductor / ASIC IP / Software Engineering
Deliverable
research
Required skills
Computer Science, Electrical Engineering, Programming (Python not mandatory), Machine Learning (bonus)
Preferred skills
LLM-based semantic reasoning, FPGA builds, Agile development
Technologies
Jira, RTL, FPGA, LLMs
