ASIC Systems Debug Engineer
Core
Lead investigations across the full product lifecycle to turn the toughest silicon and system-level failures into better products for Ericsson's custom ASICs powering 5G and 6G networks.
Role type
Senior IC ASIC Systems Debug Engineer
Builds
Reliable, high-performance silicon for baseband and radio platforms
Domain
Semiconductor / Telecommunications (5G/6G)
Required skills
ASIC/SoC system debug and root-cause analysis, complex subsystem debugging (DMA, interconnect, memory, chiplet-to-chiplet), high-speed interface expertise (DDR, Ethernet, PCIe, SerDes), silicon and system-level debug using lab equipment and trace capabilities, data analysis of production/test/field data, scripting for debug automation, silicon test and DFX concepts (ATE, scan, memory test)
Preferred skills
Technical leadership, cross-disciplinary influence, tool development
Technologies
DDR, Ethernet, CPRI, JESD, PCIe, I2C, I3C, SerDes, ATE, Scan, Memory Test
Responsibilities
Lead complex ASIC and system investigations across multiple IP and system domains, Develop structured strategies to reproduce, isolate, and characterize failures, Investigate silicon quality escapes using production, repair, test, and field-return data, Debug complex ASIC subsystems including DMA engines, interconnects, memory systems, and chiplet-to-chiplet communication, Convert technical findings into corrective actions and production-containment plans, Identify gaps in test coverage and diagnosability across environments, Create new tools, scripts, and automation to accelerate system debug, Translate debug lessons into requirements for design-for-debug features and platform observability
Seniority
Senior, hands-on IC
