Director of Buffer & Memory Subsystem Architecture
Core
Founding technical lead for HW/SW co-design of next-generation HBF–xPU systems, translating AI workload traces into architectural policies for caching, prefetching, and data movement.
Role type
Senior IC Director of Buffer & Memory Subsystem Architecture
Builds
Next-generation HBF–xPU systems for AI data centers and advanced mobile technology
Domain
Semiconductor / High Bandwidth Memory (HBM) / AI Infrastructure
Deliverable
production ML models | product features
Required skills
Memory controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, DMA/Data Movement architectures, queueing algorithms, scheduling algorithms, buffer management algorithms, system performance analysis, HW/SW co-design, functional partitioning, interface contract definition, simulation tool development
Preferred skills
Python, C/C++, SystemC, event-driven modeling, trace-driven modeling, queueing-based modeling
Technologies
Python, C/C++, SystemC
Responsibilities
Lead HW/SW co-design by defining architecture, functional partitioning, and interface contracts across the HBF hardware and software stack. Drive HBF system optimization through memory architecture, performance modeling, and system-level implementation. Develop HBF system models and event-/trace-driven simulators for AI memory performance analysis. Analyze workload performance and optimize latency, bandwidth, and memory efficiency through architecture modeling. Validate architectural assumptions and provide data-driven insights for cross-functional architecture decisions. Define HBF Memory Architecture and Policies.
Seniority
Director, founding technical lead
