(India) System IP Design Engineer
Core
Designing and optimizing power management subsystems, interrupt controllers, AXI interconnects, and cache controllers for next-generation RISC-V/ARM-based SoCs.
Role type
Senior IC RTL Design Engineer (Power Management & Subsystems)
Builds
High-performance, power-efficient RISC-V/ARM System-on-Chips (SoCs)
Domain
Semiconductor / ASIC Design / AI Hardware Infrastructure
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design (Verilog/SystemVerilog), microarchitecture definition, power management (DVFS, clocking, reset), bus protocols (AXI, AHB, APB, CHI), functional safety (ISO 26262), verification closure, synthesis, timing analysis, power optimization, LINT, CDC/RDC, power intent checks, DV tools (Verdi, NCSIM)
Preferred skills
Experience guiding junior engineers, cross-functional collaboration from concept to silicon bring-up
Technologies
RISC-V, ARM, AXI, AHB, APB, CHI, Verdi, NCSIM
Responsibilities
Own microarchitecture definition and RTL development of Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller; drive verification closure, performance debug, synthesis, timing, and power optimization; execute design-for-power, debug, and test methodologies
Seniority
Mid-Senior, hands-on IC
