Sr. Staff Engineer, RISC-V Software Workload Enablement
Core
Leading the porting and enablement of critical AI workloads to RISC-V architectures, ensuring hardware optimization for real-world application performance.
Role type
Senior Staff/Principal Engineer (RISC-V workload porting & enablement)
Builds
AI compute workloads on RISC-V hardware
Domain
AI/ML, RISC-V architecture, System Software
Deliverable
production ML models
Required skills
workload porting, DevOps engineering, application enablement, CPU architecture knowledge, systems design, performance optimization, cross-functional coordination, technical leadership
Preferred skills
ARM or x86 environment expertise, low-level OS internals knowledge, mentoring
Technologies
RISC-V, ARM, x86
Responsibilities
Migrate compute workloads to RISC-V, optimize hardware for AI application performance, coordinate across IT, DevOps, and AI teams, lead implementation of compute migration strategies
Seniority
Senior Staff/Principal, individual contributor with potential to lead a small team
