Principal FPGA / RTL Design Engineer - Signal Processing
Core
Implementing novel signal processing algorithms for MIMO wireless networking products and supporting advanced wireless systems R&D.
Role type
Principal FPGA / RTL Design Engineer (Signal Processing)
Builds
FPGA-based designs for advanced wireless systems R&D
Domain
Defense, law enforcement, public safety; MANET and MIMO communications
Deliverable
production ML models | product features
Required skills
RTL design (Verilog, System-Verilog), FPGA synthesis and timing closure, fixed-point binary arithmetic, digital signal processing (DSP), Xilinx FPGAs and SoCs, Vivado IDE, hardware verification and troubleshooting
Preferred skills
MATLAB, scripting languages (Perl, Python), wireless communication systems on FPGA or ASIC
Technologies
Xilinx, Vivado, Verilog, System-Verilog, Perl, Python, MATLAB
Responsibilities
RTL coding, simulation, and test bench development; FPGA synthesis and timing closure; hardware verification and troubleshooting; supporting RF and Software Engineering teams
Seniority
Principal, hands-on IC
