Engineering Manager - FPGA & Hardware - Enforced Security
Core
Build the FPGA discipline end-to-end for MetaDefender NetWall, a hardware-enforced unidirectional security gateway that terminates protocols and filters content in silicon to prevent back-channels.
Role type
Engineering Manager, FPGA & Hardware
Builds
Hardware datapath, protocol termination (TCP/TLS), and verification infrastructure for 100 Gbps security gateways
Domain
Cybersecurity, Hardware, FPGA, Critical Infrastructure
Required skills
RTL architecture, verification strategy, timing closure, IP licensing, silicon/board selection, vendor management, team building, UVM, formal proof
Technologies
FPGA, RTL, UVM, PCIe, TCP, TLS, COTS cards
Responsibilities
Own the FPGA discipline (RTL, verification, timing, IP, build infrastructure); Select silicon and boards (FPGA families, COTS cards, transceivers); Build one-way datapath in gateware (framing, link supervision, fail-closed); Move protocol termination into hardware (TCP state machines, TLS termination); Own verification (UVM, constrained-random regression, coverage closure, formal proof)
Seniority
Manager, hands-on IC
