Senior Engineer, HIG-HBM Product Engineering (Media Health Reliability)
Core
Define and develop reliability stress test flows and plans for HBM products, drive DPM reduction, and perform root cause analysis on device failures using electric and physical failure analysis.
Role type
Senior IC reliability engineer (semiconductor)
Builds
HBM memory products and qualification test flows
Domain
Semiconductor manufacturing and reliability engineering
Deliverable
production ML models
Required skills
Electric Failure Analysis (EFA), Physical Failure Analysis (PFA), CMOS technology, DRAM architecture, data analysis, statistics, Python, JMP, root cause analysis, project management
Preferred skills
Semiconductor device physics, circuit design, product validation, AI/ML for reliability (regression, classification, anomaly detection, clustering), agentic AI, Claude code
Technologies
Python, JMP, Claude code, agentic AI platforms
Responsibilities
Define reliability stress test flows and plans; manage qualification execution and gating issue resolution; drive DPM reduction via optimized test strategies; debug and resolve defectivity and intrinsic reliability issues; provide recommendations for fab process conversions; manage risks associated with DPM process conversions; apply machine learning to reliability datasets to segment fails and outliers; embed AI/automation into reliability workflows.
Seniority
Senior, hands-on IC
