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PI PTO Engineer

Boise, Idaho, United States of America💼 Full-time🗓 2026-09-28 → 2026-10-07

Core

Manage part type introductions, wafer resource planning, and yield performance across all manufacturing stages for semiconductor products.

Role type

Senior IC Process Integration Engineer (NPI/Yield)

Builds

New DRAM/NAND product introductions and sustained production lines (via careerplan.io/jobs/44700592-pi-pto-engineer-at-micron)

Domain

Semiconductor manufacturing (DRAM/NAND)

Required skills

DRAM/NAND technologies, Statistical Process Control (SPC), Project Management, Engineering Data Analytics, NPI/Product Transfer, Yield optimization, Risk Management, Resource and Process Optimization

Technologies

SPACE, JMP, Power BI, SQL

Responsibilities

Execute system and traveler setup for pilot scheduling; project yield curves to support business planning; manage B-type wafer requirements for pilot runs; coordinate with planning and operations teams to manage priority lots; oversee attribute settings and system configurations; collaborate with reticle engineers to track new reticle deliveries.

Seniority

Mid-Senior, hands-on IC