SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)
Core
Lead end-to-end validation of clock, power, reset, and power-management architectures for next-generation AI accelerator platforms, ensuring robust operation under demanding AI training and inference scenarios.
Role type
Staff SoC Clock & Power Management Validation Lead
Builds
Production-quality silicon for AI accelerator platforms across mobile, data center, and AI segments
Domain
Semiconductor / AI Accelerator / SoC Validation
Deliverable
production ML models
Required skills
SoC validation, Clocking, DVFS, Power Management, PMIC, Silicon Bring-up, C, Python, Lab instruments (multimeter, oscilloscope, logic analyzer), Debug methodology (JTAG, ARM SoC)
Preferred skills
FPGA-based emulation validation, RTL/Verilog/System Verilog, Cross-compilers/Linkers, Coherency and concurrency in SoC architecture, Rail power validation
Technologies
Python, Perl, Shell, C, JTAG, ARM SoC, FPGA, Verilog, System Verilog
Responsibilities
Own E2E bare metal framework validation for SoC clock and power architectures; Develop scalable device drivers and system tests in C; Automate validation processes using Python, Perl, and Shell; Debug complex pre-Si and post-Si power, performance, and stability issues; Review validation platform schematics for post-Si debug support; Conduct validation strategy reviews with stakeholders.
Seniority
Staff, hands-on IC
