SOC Clock & Power Management Validation Engineer, Staff
Core
System-level validation of clock, power, reset, and power-management architectures for next-generation Premium Tier MSM platforms, ensuring end-to-end silicon quality across pre- and post-silicon phases.
Role type
Staff IC SoC validation engineer (clock & power management)
Builds
Production-quality silicon for Premium mobile, flagship, data center, and AI Accelerator platforms
Domain
Semiconductor / SoC Design & Validation
Required skills
SoC validation, Clocking architecture, DVFS, Power Management, PMIC integration, Silicon bring-up, Bare-metal validation, C programming, Python scripting, Lab instrumentation (multimeter, oscilloscope, logic analyzer), Debug methodology (JTAG, ARM SoC)
Preferred skills
FPGA-based emulation validation, RTL/HDL (Verilog/System Verilog), Cross-compilers/Linkers, Coherency and concurrency in SoC, Rail power validation
Technologies
C, Python, Perl, Shell, JTAG, ARM SoC, FPGA, Verilog, System Verilog
Responsibilities
Own E2E bare-metal framework validation for SoC clock and power architectures; Develop scalable device drivers and system tests; Debug complex pre-Si and post-Si power/performance/stability issues; Automate validation processes; Review validation platform schematics for debug support.
Seniority
Staff, hands-on IC with strategy & mentorship
