CPU Architecture Validation Infrastructure Engineer
Core
Design, optimize, verify, and test CPU subsystem validation infrastructure across bare-metal and OS-based full-stack environments (TFA, Linux, hypervisor, TEE) to support custom CPU features, low-power, and DVFS capabilities.
Role type
Senior IC CPU Architecture Validation Infrastructure Engineer
Builds
CPU validation infrastructure and firmware for next-generation mobile and connected devices
Domain
Semiconductor / CPU Microarchitecture
Required skills
CPU microarchitecture (ARM v8/v9), low-level firmware, Caches/MMU/interrupts/debug subsystems, RTOS/Linux kernel/hypervisors/device drivers, bring-up and debugging in complex environments
Preferred skills
ARM v9 architecture, Trusted Firmware-A (TFA)
Technologies
TFA, Linux, Hypervisor, TEE, FPGA, DSP
Responsibilities
Develop and maintain CPU subsystem validation infrastructure; Execute and debug functional validation for custom CPU features; Enable and validate low-power and DVFS features; Debug and profile support across bare-metal and full-stack environments
Seniority
Senior, hands-on IC
