Engineer/Senior Engineer, STPG PE (FDV-Infrastructure)
Core
Design and execute functional and design validation flows for advanced RG NAND devices using silicon platforms, focusing on automation, data-driven validation, and AI-assisted techniques to improve test efficiency and debug productivity.
Role type
Senior IC silicon validation and test infrastructure engineer
Builds
Test program infrastructure, automation frameworks, and data-driven validation flows for NAND memory products
Domain
Semiconductor / Memory / Silicon Validation
Required skills
C/C++, Python, Perl, ATE test program development, electrical failure analysis, root cause analysis, data analytics, pattern recognition, anomaly detection
Preferred skills
Experience with Teradyne or Advantest, memory products, digital and analog circuitry
Technologies
C, C++, Python, Perl, ATE (Teradyne, Advantest)
Responsibilities
Design and execute functional and design validation flows for advanced RG NAND devices; Develop and maintain test program infrastructure including deterministic usage-case tests and random sequence generators; Implement automation frameworks to improve test development and execution efficiency; Apply AI/ML-assisted techniques for failure triage, coverage gap identification, and debug prioritization; Utilize data-driven methods and dashboards to track validation progress and defect trends; Perform electrical failure analysis and root cause investigations for digital and analog circuitry issues
Seniority
Senior, hands-on IC
