CareerPlan

Sr Design Readiness Engineer

Boise, Idaho, United States of AmericaFull-time2026-09-02 → 2026-11-10

Core

Lead design readiness activities for new DRAM products, including risk assessments, validation planning, and root-cause investigations of silicon findings.

Role type

Senior IC design readiness engineer (DRAM)

Builds

New DRAM memory products

Domain

Semiconductor / Memory Technology

Required skills

DRAM design, silicon validation, device characterization, circuit debug, reliability engineering, test development, root-cause analysis, statistical methods, cross-functional leadership

Preferred skills

PhD or MS in relevant field, mentoring engineers, silicon debug, production test coverage, margin characterization, AI proficiency, Agentic AI tools

Technologies

DRAM, Silicon, Validation Tools, AI-enabled tools