Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)
Core
Lead the development of specialized analog components, focusing primarily on clocking (PLL, DLL, CDR) and transmitter/receiver circuits for high-speed chip-to-chip and memory interconnect.
Role type
Principal Analog Design Engineer (Mixed-Signal PHY)
Builds
Custom and original analog circuits for high-speed signaling
Domain
Semiconductor / High-Speed Interconnect / Memory
Required skills
Transistor-level circuit design, PLL/DLL/CDR architecture, HSpice simulation, Process corner analysis, Monte Carlo analysis, Jitter analysis, Yield-aware development
Preferred skills
High-speed transmitter development, Receiver development (sense amplifiers, CTLE/DFE), Die-to-die PHY architectures, OTP/fuse-based calibration, Post-silicon characterization
Technologies
HSpice, CMOS nodes, PLL, DLL, CDR, SerDes, UCIe, AIB, BoW
Responsibilities
Lead development of specialized analog components (clocking, TX/RX), Contribute to top-level PHY analog architecture decisions, Build and maintain transistor-level simulation testbenches, Define interface specifications between analog blocks and digital control, Collaborate with layout team for custom analog layout and post-silicon characterization
Seniority
Principal, hands-on IC