Senior/Principal Eng, FE OCT CPEE PHOTO EUV/DUV PROCESS
Core
Lead HVM photo yield, quality, productivity, and cost improvement initiatives while resolving complex photo process issues through data-driven root-cause analysis.
Role type
Senior/Principal Front-End Process Engineer (Photolithography)
Builds
Memory and storage solutions (DRAM, NAND, NOR) for data centers, AI, 5G, and mobile applications
Domain
Semiconductor manufacturing (Photolithography)
Deliverable
production ML models
Required skills
Semiconductor photolithography, yield improvement, root-cause analysis, Best Known Methods (BKM) deployment, cross-fab alignment, supplier management, data-driven problem solving
Preferred skills
AI tool integration, global team collaboration, business travel
Technologies
EUV, DUV, overlay, CDU, metrology, reticle correction, destack, yield matching
Responsibilities
Lead HVM photo yield, quality, productivity, and cost improvement initiatives; Resolve complex photo process issues (overlay, CDU, EPE, MMM, destack, RWC, yield matching) through data-driven root-cause analysis; Define and deploy Photo Process Best Known Methods (BKM) across fabs for HVM and NPI; Act as the technical point for cross-fab, complex lithography customer concerns; Drive MOR–POR gap closure and cross-fab/node alignment; Influence key suppliers and represent OCT Photo in reviews, workshops, and governance forums
Seniority
Senior (5+ years) or Principal (8+ years), hands-on IC