CareerPlan

DRAM Device & Process Modeling Engineer

Boise, Idaho, United States of AmericaFull-time2026-08-12 → 2026-11-10

Core

Driving front-end process integration for future DRAM technology nodes using device and process modeling to guide integration decisions and shorten learning cycles.

Role type

Senior IC process integration engineer (DRAM R&D)

Builds

Future DRAM technology nodes for AI-enabled customers

Domain

Semiconductor manufacturing / Memory technology

Deliverable

production ML models

Required skills

Semiconductor process integration, Device physics, TCAD/Silvaco/Sentaurus simulation, DOE design and analysis, Silicon data correlation, Root cause analysis

Preferred skills

PhD in EE/Physics/Materials Science, Advanced-node integration experience, Technology transfer experience, Predictive model calibration

Technologies

TCAD, Silvaco, Sentaurus

Responsibilities

Define integration schemes and drive unit process/module interactions; Design and execute DOEs on silicon; Correlate simulation results with experimental data; Work cross-functionally to resolve technical issues; Support transfer from R&D to manufacturing

Seniority

Senior, hands-on IC