OMT RAM RDA Process Optimization Engineer
Core
Use process and defect simulation to identify root causes of defects and optimize process windows to improve yield and reliability in semiconductor manufacturing.
Role type
Process Optimization Engineer (Semiconductor Yield Engineering)
Builds
High-performance DRAM, NAND, and NOR memory and storage products
Domain
Semiconductor manufacturing (Memory/Storage)
Deliverable
production ML models
Required skills
Process defect root cause analysis, Process simulation modeling, Data correlation (inline defect, EBI, yield), What-if simulation, Structured problem-solving (FA, FMEA, DOE, SPC, 8D), New Process Introduction (NPI) assessment (via careerplan.io/jobs/41005426-omt-ram-rda-process-optimization-engineer-at-micron)
Preferred skills
TCAD and process simulation tools, Yield modeling, Defect density analysis, Statistical modeling, Semiconductor change management
Technologies
TCAD, SPC, Inline metrology, Defect inspection tools
Responsibilities
Develop and apply process/defect simulation models to understand defect generation mechanisms; Correlate simulation results with manufacturing data to identify true root causes; Drive data-backed strategies to expand process windows; Perform what-if simulations for parameter/material/equipment changes; Partner with cross-functional teams to implement fab actions; Lead defect reduction and yield improvement projects; Support NPI and baseline qualification via modeling; Document models and improve simulation methodologies
Seniority
Mid-Senior, hands-on IC