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Netanya, IsraelFull-time2026-09-17 → 2026-10-08

Core

Lead design for testability (DFT) efforts to ensure optimal manufacturing and quality assurance processes for complex electronic systems.

Builds

Production test programs and strategies for electronic products and PCB assemblies

Domain

Semiconductor / Electronic Design

Required skills

DFT methodologies, scan, BIST, boundary scan, digital design, VLSI design flow, verification processes, test coverage analysis, ATE requirements

Preferred skills

Mentor Graphics Tessent, Synopsys DFTMAX, Cadence Modus, TestWay, JTAG/Boundary Scan test development, technical leadership

Technologies

Mentor Graphics Tessent, Synopsys DFTMAX, Cadence Modus, TestWay, JTAG, ICT, Flying Probe

Responsibilities

Implement DFT methodologies, review schematics and PCB layouts, collaborate with hardware design teams, perform test coverage analysis, define manufacturing test strategies, develop and execute JTAG/Boundary Scan tests, lead test pattern generation and troubleshooting, resolve DFT-related issues, define ATE requirements, provide technical leadership and mentorship

Seniority

Senior, hands-on IC