Senior Digital IC Design Engineer
Core
Designing ultra-low-power, high-density cryogenic control ICs for fault-tolerant quantum computing scale-out, addressing interconnect bottlenecks in sub-Kelvin systems.
Role type
Senior Digital IC Design Engineer (Front-End & Back-End)
Builds
Cryogenic digital logic blocks and control sub-circuits for quantum processors
Domain
Quantum Computing / Cryogenic CMOS / Semiconductor Design
Required skills
Digital IC design, Mixed-signal IC design, RTL development (Verilog/SystemVerilog), AMS Co-simulation, Physical Implementation (PnR/CTS), Low-power synthesis, Static Timing Analysis (STA), Physical signoff (DRC/LVS/ERC), High-speed serial interconnect protocols, Finite-state machine (FSM) design, Low-power dissipation techniques
Preferred skills
Cryogenic CMOS experience (sub-4.2 K), Mixed-signal & AMS interfaces (ADCs/DACs), Quantum architecture awareness, Power-aware simulation (UPF/CPF), Advanced process nodes (sub-28nm, FD-SOI, FinFET), EDA scripting (TCL/Python), DFT & Silicon Bring-Up
Technologies
Cadence Virtuoso/Innovus/Xcelium, Synopsys Design Compiler, Voltus, PrimePower, IEEE 1801 UPF/CPF
Responsibilities
Microarchitecture specification, RTL development, Verilog-AMS co-simulation, Physical implementation, Low-power synthesis, Static timing analysis, Tape-out signoff
Seniority
Senior, hands-on IC
