Ph.D. Intern - Architecture, DSP & Systems Architecture
Core
Architecting systems-level designs for AI infrastructure, including switching, interconnect, and DSP applications for hyperscale data centers.
Role type
Ph.D. Intern, Systems Architecture & DSP
Builds
AI interconnect hierarchy (scale-up networks, Teralynx Ethernet switch family, DCI platforms)
Domain
Semiconductor, AI Infrastructure, High-Speed Networking
Deliverable
production ML models | product features | dashboards & analysis
Required skills
Computer architecture, Digital signal processing, Networking algorithms, System-level modeling and simulation, Analytical fundamentals (signal processing theory, queuing theory, information theory), MATLAB/Python/C++ simulation
Preferred skills
Ethernet switching architectures, Programmable forwarding pipelines, Network congestion control, PAM4/Coherent DSP, Custom compute architecture (SoC/XPU), Ultra Ethernet Consortium protocols, Open networking platforms (SONiC, P4)
Technologies
PCIe, UAL, NVLink, Teralynx, PAM4, Coherent, MATLAB, Python, C++, Verilog, SystemVerilog
Responsibilities
Architect, model, and evaluate system-level designs for switching, interconnect, or DSP applications; Develop and optimize DSP algorithms for high-speed electrical or optical links; Design and analyze network architectures for AI fabrics; Collaborate with analog, digital, and software engineering teams to validate architectural assumptions; Build behavioral models and simulations to evaluate performance tradeoffs; Present architectural proposals and algorithm results to engineering leadership
Seniority
Intern, Research-focused
