Test Engineering Director
Core
Oversee test engineering strategy for IO Chiplet-based silicon semiconductor chips targeting high-speed and high-power AI applications, ensuring no underperforming units are shipped.
Role type
Director of Test Engineering (Operations)
Builds
Scalable ATE IP, software frameworks, automation methodologies, and production manufacturing flows for advanced semiconductor products.
Domain
Semiconductor / High-speed IO / AI Infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ATE platform selection, vendor engagement, cross-functional team leadership, ATE architecture definition, CAPEX/OPEX planning, yield analytics, failure analysis, load board design, signal integrity optimization, Python/C/C++/Java development
Preferred skills
High-speed IO and die-to-die interface characterization (PCIe, Serdes, UCIe, HBM, CXL), advanced packaging technologies (MCM, CPC, CPO), wafer probe hardware design, high-speed digital test methodologies (up to 100GHz), chip-to-chip communication protocols, automated test platforms (Advantest 93K, Teradyne UltraFLEX)
Technologies
Advantest 93K, Teradyne UltraFLEX, Python, C/C++, Java, PCIe, Serdes, UCIe, HBM, CXL, I2C, SPI, JTAG, MDIO
Responsibilities
Define and lead overall test engineering strategy for IO Chiplet-based products; Drive strategic partnerships with Tier 1 ATE vendors and OSATs; Lead cross-functional engineering teams to develop robust test infrastructure; Build and manage teams responsible for customer sample validation and yield improvement; Architect scalable and reusable ATE IP and automation methodologies; Lead ATE hardware architecture and system verification; Drive continuous improvement initiatives for test cost reduction and throughput optimization.
Seniority
Director, strategic leadership & hands-on technical architecture
