Analog IC Design Engineer, Senior Staff Engineer
Core
Lead a team of analog design engineers to develop and deliver high-performance CMOS transceiver, SERDES, and PLL IP from concept to production.
Role type
Senior Staff Analog IC Design Engineer (Team Lead)
Builds
High-speed CMOS transceiver, SERDES, PLL, DLL, ADC, and regulator IP for data infrastructure
Domain
Semiconductor / Analog IC Design / High-Speed SerDes
Deliverable
production ML models | product features
Required skills
PLL/DLL/ADC/regulator/amplifier design, 112G+ SerDes (short reach/low power), Single-ended High Density Parallel Interface (UCIe, DDR5/LPDDR5, GDDR6/LPDDR6), analog design/verification tools (Virtuoso, Spectre, ADE), signal integrity/noise reduction, Multi-GHz low-jitter clock generation, FinFet layout, system-level pre-tape out validation, lab chip bring-up/debugging
Preferred skills
Experience with high-speed SerDes, knowledge of UCIe/DDR5/GDDR6 standards
Technologies
Virtuoso, Spectre, ADE, SPICE, MATLAB
Responsibilities
Lead analog design team, interface with layout/verification/application teams, manage IP delivery from concept to production, perform architectural investigations and circuit implementation, conduct design verification
Seniority
Senior Staff, hands-on IC design with team leadership
