Senior Principal Engineer -RTL
Core
Sub-system Architect defining end-to-end architecture for advanced SoCs, optimizing for reuse, performance, power, and security across enterprise, cloud, AI, and automotive domains.
Role type
Senior Principal IC Sub-system Architect (RTL/Architecture)
Builds
Advanced System-on-Chips (SoCs) for data infrastructure, enterprise, cloud, AI, automotive, and carrier architectures
Domain
Semiconductor / ASIC Design / Computer Architecture
Deliverable
production ML models | product features
Required skills
Verilog/System Verilog RTL coding, System Verilog assertions, ASIC design flow expertise, subsystem and block-level architecture, third-party IP integration (Synopsys, Cadence, ARM), interconnect fabrics (Arm, Arteris, AXI/APB, NoC), peripheral interface protocols (I3C, I2C, SPI, UART, GPIO, USB), Perl/Python/Shell scripting
Preferred skills
Experience with complex chips (network processors, CPUs, GPUs, Switches, Machine Learning SoCs), mentorship of junior engineers
Technologies
Synopsys, Cadence, ARM, Arteris, System Verilog, Perl, Python, Shell
Responsibilities
Own future roadmap and execution of subsystem architecture, define KPIs and make technical trade-offs, define architecture specs and PRDs, partner on verification strategy and methodologies, collaborate with SoC Chief Engineers and cross-functional teams
Seniority
Principal, hands-on IC with strategic ownership
