Staff QA Engineer (DDR, CXL, PCIE)
Core
Design and implement advanced automation frameworks to validate firmware for PCIe, CXL, memory controller products, and integrate quality processes into CI/CD pipelines.
Role type
Staff QA Engineer (Hardware/Firmware Validation)
Builds
Robust, high-quality releases of management subsystem and CXL, memory and interconnect technologies
Domain
Semiconductor, Data Infrastructure, High-Speed Interconnects (PCIe, CXL, DDR)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Python, C/C++, Pytest, GTest, PCIe protocol, CXL protocol, NVMe protocol, SSD architecture, Firmware testing, CI/CD integration, Protocol analyzer setup, Trace analysis, Debugging, OOP concepts
Preferred skills
Open-source AI tools, Prompt engineering, Robot Framework, Storage benchmarking, Management protocols (MCTP, Redfish, NVMe-MI)
Technologies
Pytest, GTest, Jenkins, GitLab CI, GitHub Actions, Protocol Analyzers
Responsibilities
Write new unit/integration tests from scratch for Python and C/C++ modules; Use Pytest and GTest frameworks to add or modify test cases; Perform basic debugging for failed tests and automation issues; Understand how automated tests run within a CI/CD pipeline; Set up protocol analyzers, capture traces, and analyze traces; Analyze firmware logs to identify issues
Seniority
Staff, hands-on IC with leadership
