Spring 2027 - Top Drain TFET for HV AND GPU enabled atomistic simulations Internship
Core
Evaluate top-drain TFET options, model sense devices using TCAD and multiphysics tools, and perform atomistic simulations for NVM candidate devices.
Role type
Research intern (device physics & simulation)
Builds
Research insights and device models for smart power and next-generation memory
Domain
Semiconductor industry, device physics, computational modeling
Deliverable
research
Required skills
TCAD simulation, Multiphysics modeling, Atomistic simulations, Device characterization, Layout design, White paper writing
Preferred skills
None stated
Technologies
TCAD tools, Multiphysics tools
Responsibilities
Evaluate options for top-drain TFET, Model sense device for smart power, Create white paper evaluating TFET up-drain devices and tradeoffs, Perform atomistic simulations for NVM candidate devices, Conduct electrical characterization of devices, Perform layout work for next generation devices
