ASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 12+ years, Bangalore
Core
Lead full-chip electrical architecture and mixed-signal design for high-speed silicon photonics driver ICs (100G/200G/400G per lambda) supporting Cisco's core data center networking solutions.
Role type
Senior IC analog/mixed-signal design leader (silicon photonics)
Builds
High-speed pluggable and Co-packaged Optics (CPO) transceivers and modules
Domain
Data center networking / Silicon photonics / High-speed optical transceivers
Deliverable
production ML models | product features | infrastructure
Required skills
High-speed analog/mixed-signal IC design, Modulator drivers, TIAs, CDRs, PLLs, ADC/DAC, Cadence Virtuoso, Spectre, Calibre, Verilog/SystemVerilog, Python or C scripting, Tapeout cycle leadership
Preferred skills
Silicon photonics driver ICs, Direct-detect optical architectures, High-speed PHYs and protocols (112G/224G PAM4 SerDes, Ethernet, UCIe), Design for testability (DFT), High-speed measurement equipment (BERTs, oscilloscopes), SI/PI analysis, PCB/test fixture design
Technologies
Cadence Virtuoso, Spectre, Calibre, Verilog, SystemVerilog, Verilog-AMS, Python, C, BERTs, Oscilloscopes, Communication analyzers
Responsibilities
Lead full-chip electrical architecture and specifications for silicon photonics driver ICs, Own end-to-end mixed-signal design for transmit and receive paths, Design and optimize critical building blocks (modulator drivers, TIAs, serializers, PLLs), Drive performance across power, speed, signal integrity, testability, and cost, Define and execute verification and validation strategies, Lead silicon bring-up, debug, and lab validation, Mentor engineers across analog, digital, and validation domains
Seniority
Senior, hands-on IC leader with mentorship responsibilities
