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ASIC Engineering Technical Leader

Nuremberg, Germany💼 Full-time🗓 2026-05-22 → 2026-07-31

Join Cisco’s High-Speed Optics team—an innovative group dedicated to advancing the design, integration, and validation of cutting-edge optical modules and interfaces. Our team’s work is vital to Cisco’s leadership in high-speed networking, powering the backbone of data centers and enterprise optical networks worldwide. With a diverse, highly skilled group of engineers, we foster an open, collaborative, and intellectually curious environment where every voice is valued. We are passionate about pushing boundaries, driving new technological frontiers, and shaping the future of optical communications. If you thrive in a dynamic and forward-thinking setting, you’ll find this team both inspiring and rewarding.

Responsibilities

  • Architect, design, layout, measure, and productize high-speed TIA and Driver in CMOS process.
  • Lead efforts for a complex chip, mentor team members, and track deliverables.
  • Participate in peer review of complex IC designs and provide solid design methodology from conception to production.
  • Collaborate with packaging and hardware design teams to ensure signal and power integrity specifications are met.
  • Define the qualification and wafer test for the designs.

Requirements

  • BSEE degree with 12+ years of experience or equivalent, OR an MS degree with 8+ years of experience or equivalent, OR a PhD with 5+ years of experience or equivalent.
  • Design, simulation, and measurement of:

* High-speed ICs such as: Transimpedance Amplifiers, Linear drivers, Programmable gain amplifiers, and equalization techniques.

* Basic Analog circuits such as: Biasing circuits, voltage regulators, Opamps.

Nice to Have

  • Experience with electrical transceiver applications including backplane and cable communications.
  • Experience with CMOS and FinFET technology.
  • High-frequency layout experience: Passive component design (inductors, transformers, transmission-lines, etc.).
  • Floor planning experience (power/ground, digital/analog signal routing, etc.).
  • Custom transistor layout experience.
  • Experience designing for manufacturability.
  • Experience with Cadence (Virtuoso), Spectre/APS/SpectreX, Matlab, EMX.

Benefits

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Rewrite
## About the Team Join Cisco’s High-Speed Optics team—an innovative group dedicated to advancing the design, integration, and validation of cutting-edge optical modules and interfaces. Our team’s work is vital to Cisco’s leadership in high-speed networking, powering the backbone of data centers and enterprise optical networks worldwide. With a diverse, highly skilled group of engineers, we foster an open, collaborative, and intellectually curious environment where every voice is valued. We are passionate about pushing boundaries, driving new technological frontiers, and shaping the future of optical communications. If you thrive in a dynamic and forward-thinking setting, you’ll find this team both inspiring and rewarding. ## Responsibilities * Architect, design, layout, measure, and productize high-speed TIA and Driver in CMOS process. * Lead efforts for a complex chip, mentor team members, and track deliverables. * Participate in peer review of complex IC designs and provide solid design methodology from conception to production. * Collaborate with packaging and hardware design teams to ensure signal and power integrity specifications are met. * Define the qualification and wafer test for the designs. ## Requirements * BSEE degree with 12+ years of experience or equivalent, OR an MS degree with 8+ years of experience or equivalent, OR a PhD with 5+ years of experience or equivalent. * Design, simulation, and measurement of: * High-speed ICs such as: Transimpedance Amplifiers, Linear drivers, Programmable gain amplifiers, and equalization techniques. * Basic Analog circuits such as: Biasing circuits, voltage regulators, Opamps. ## Nice to Have * Experience with electrical transceiver applications including backplane and cable communications. * Experience with CMOS and FinFET technology. * High-frequency layout experience: Passive component design (inductors, transformers, transmission-lines, etc.). * Floor planning experience (power/ground, digital/analog signal routing, etc.). * Custom transistor layout experience. * Experience designing for manufacturability. * Experience with Cadence (Virtuoso), Spectre/APS/SpectreX, Matlab, EMX. ## Benefits At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.
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