Electrical Post-Silicon Characterization & Validation Engineer
Core
Lead hands-on lab debugging and ASIC bring-up for high-speed networking chips, focusing on SerDes, power/clock domains, and PVT characterization to fix silicon performance and yield issues.
Role type
Senior IC electrical post-silicon validation engineer
Builds
Networking chips (SerDes, high-speed interfaces)
Domain
Semiconductor hardware validation / Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC bring-up, SerDes testing, board probing, PVT characterization, Python automation, signal integrity analysis, power integrity analysis, yield improvement, hardware debugging, test equipment operation
Preferred skills
System-level debugging, PCB/package debugging, global team collaboration, technical ownership
Technologies
Python, VNAs, TDRs, phase noise analysers, scopes, EVBs
Responsibilities
Lead hands-on lab debugging for silicon performance and yield issues, Lead ASIC bring-up on validation boards, Run characterization across PVT conditions, Write and optimize Python code to automate lab equipment, Define validation methodologies and advanced lab measurement techniques
Seniority
Senior, hands-on IC
