ASIC High Speed AMS Technical Leader
Domain
Silicon Photonics, High-speed optical transceivers, Data center networking, AI/ML workloads
Technologies
Cadence Virtuoso, Spectre, Caliber, SystemVerilog, Verilog-AMS, Python, C, SerDes 112Gbps/224Gbps PAM4, Ethernet, UCIE, IEEE 802.3 specifications, QSFP/QSFP-DD, MSA standards, Verilog-A modeling
Responsibilities
Lead full-chip electrical specifications, circuit design, and verification test plans, Author mixed-signal datapath designs including photonics modulator drivers, serializers, PLLs, TIAs and control circuits, Debug complex silicon and system-level issues during bring-up and lab validation, Mentor and guide analog, digital, and validation engineers
Seniority
Technical Leader, 12+ years experience (Bachelor's), 8+ years (Master's), 5+ years (PhD)
Required skills
High-speed AMS design, Analog/mixed-signal design, Optical transceiver design (modulator drivers, TIA, CDR, PLLs, ADC/DAC), Tapeout cycle leadership, Design automation scripting
Preferred skills
10-15 years analog/mixed signal experience, Silicon photonics driver ICs experience, DFT and test methodology development, Lab instrumentation experience (digital communication analyzers, real-time scopes, BERTs), Optical sub-component models familiarity