Component Engineer Hybrid, San Jose, CA
Required skills
BS/MS in Electrical Engineering, Computer Engineering, or related fields, 5+ years experience in memory design/application OR Field Application Engineering, Strong familiarity with JEDEC memory standards, Strong knowledge of DRAM ECC methodologies, including Partial Chipkill (PCLS) and Single Device Data Correction (SDDC) techniques, Knowledge of various DRAM types (e.g., DDRx, HBM) used in server and networking applications
Preferred skills
Strong problem-solving skills and effective conflict resolution abilities, Experience with semiconductor device reliability testing and characterization methods, such as HTOL, ELFR, LU and ESD, Experience in investigating component failures across NPI, mass production, and field returns, with knowledge of FA techniques
Technologies
DRAM, DDRx, HBM, JEDEC memory standards, DRAM ECC methodologies, Partial Chipkill (PCLS), Single Device Data Correction (SDDC)
Responsibilities
Collaborate with Cisco’s design teams to enhance and improve memory reliability, availability, and serviceability (RAS) features across Cisco platforms, Support supply chain and quality teams with technical expertise for supplier and component evaluations, Lead investigations and end-to-end failure analysis for components and system issues, working with vendors to define, implement, and verify corrective and preventive actions (8D, RCA, etc.)
Seniority
Not specified
Domain
Memory technologies, component quality, semiconductor reliability, supply chain, design engineering