FE RTL Infrastructure - CAD Engineer
Core
Design and maintain infrastructure, version control, and configuration management systems for RTL design and verification teams, while integrating generative AI solutions to accelerate engineering productivity.
Role type
Senior IC infrastructure engineer (RTL/CAD)
Builds
Reliable RTL design/verification infrastructure, version control ecosystems, and centralized configuration management systems
Domain
Semiconductor hardware design (RTL) + Software infrastructure
Deliverable
infrastructure
Required skills
Python, Perl, Verilog, SystemVerilog, Perforce administration, generative AI integration, configuration management
Preferred skills
Front-End EDA tools (CDC, RDC, Lint), RTL build flows, large-scale software system development, MSEE/CE/CS degree
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