RFIC Design Engineer
Core
Architect, design, and validate radio transceivers integrated into wireless System-on-Chips (SoCs) to deliver high-performance wireless connectivity solutions.
Role type
Senior IC RFIC Design Engineer
Builds
Radio transceiver building blocks and chains (TX, RX, PLL-LOGen) for wireless SoCs
Domain
Wireless silicon development, RF/Analog architecture, VLSI
Required skills
Analog design concepts (noise, linearity, mismatch, stability), RF circuit design (LNAs, PAs, PLL/VCO, mixers, filters, data converters), Cadence Virtuoso, Spectre RF, EM simulation (HFSS, EMX), Silicon characterization and debugging
Preferred skills
Wireless transceiver mass production experience, RF transceiver architecture trade-offs, Modulation impact on radio architecture, Mixed-signal verification (SystemVerilog, AMS)
Technologies
Cadence Virtuoso, Spectre RF, Matlab, HFSS, EMX, SystemVerilog, AMS
Responsibilities
Provide RFIC designs from concept to transistor-level feasibility studies and actual design; Design and deliver radio transceiver building blocks and chains; Collaborate with RF Systems on block-level specifications and spec margin distribution; Design RF and Analog loopbacks for calibration; Address Co-Existence scenarios; Collaborate with test engineers on chip debugging and optimization; Provide design versus silicon measurements correlation for volume production
Seniority
Senior, hands-on IC
