Modeling Architect
Core
Hands-on architecture modeling for the T100 optical inference accelerator, performing hardware/software co-design to validate performance, power, and functional correctness of AI inference workloads.
Role type
Senior IC modeling architect (hardware/software co-design)
Builds
Functional, performance, and power models of compute blocks, memory hierarchies, and hardware/software interfaces for optical inference accelerators.
Domain
AI hardware / Silicon photonics / Computer architecture
Deliverable
production ML models
Required skills
Python, C++ (C++17+), computer architecture, microarchitecture, roofline analysis, Hugging Face, PyTorch, event-driven simulation, SystemVerilog, RTL simulation, memory hierarchies (HBM, SRAM, DRAM), ISA design, debugging
Preferred skills
PhD in EE/CS/CE, GPU benchmarking, cycle-accurate simulation (gem5, SystemC), NoC/AXI/DMA experience, CUDA, PyTorch internals
Technologies
Python, C++, SystemVerilog, Verilator, Hugging Face, PyTorch, gem5, SST, CUDA
Responsibilities
Bind Hugging Face and PyTorch workloads to the programming model and run them on functional models; Co-design tiling, scheduling, ISA, and memory hierarchies; Build layers of the modeling stack including Python energy/latency models and C++ functional models; Own tests, configs, and plots to ensure reproducibility; Use coding agents for multi-file edits and review generated C++/SystemVerilog; Share results with compiler, runtime, and RTL teams.
Seniority
Senior, hands-on IC
