Senior Silicon Validation Engineer
Core
Develop validation strategy, requirements, environments, tools, and methodologies for post-silicon validation, triage, and debug of SoC and platform functionality.
Role type
Senior Silicon Validation Engineer
Builds
Post-silicon validation plans, test content, scripts, tools, and verification collateral for CPU, SoC, and IP development teams.
Domain
Semiconductor / Computer Architecture / SoC Validation
Required skills
SoC validation principles, Python/C/C++ scripting, post-silicon validation leadership, cross-disciplinary taskforce management, high-speed IO (Ethernet, PCIe), board level schematics, system level software/firmware, hardware/software debug, on-chip debug (trace, JTAG), test equipment usage (protocol analyzers, logic analyzers, oscilloscopes)
Preferred skills
Pre-silicon verification planning, architecture influence, mentorship
Technologies
Python, C/C++, JTAG, trace, protocol analyzers, bit error rate testers, logic analyzers, high speed oscilloscopes
Responsibilities
Develop validation strategy and methodologies; write and implement test plans; execute post-silicon validation and debug failures; provide technical guidance and mentorship; collaborate with architects and verification engineers; drive continuous improvement in design and validation plans.
Seniority
Senior, hands-on IC with leadership responsibilities
