Senior SoC HW (Power Management) Validation Engineer
Core
Own post-silicon validation and debug of Power Management features across CPU cores, mesh, memory, I/O, package, and platform power domains to ensure robust, efficient, and scalable power management solutions.
Role type
Senior IC SoC HW Validation Engineer (Power Management)
Builds
Post-silicon validation strategies, debug tools, telemetry solutions, and automation frameworks for power states, DVFS, idle/active power management, and thermal management.
Domain
Semiconductor / SoC Hardware / Power Management
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC system-level validation, Python/C/C++ scripting, root-cause analysis of silicon/firmware/hardware issues, validation requirements definition, test plan creation, automation framework development, telemetry analysis, pre-silicon platform experience (emulation/FPGA), hardware/software debug, board-level schematic understanding, synthetic SoC content development.
Preferred skills
Analog validation experience, logic development experience, leadership in validation techniques, mentoring capabilities, continuous improvement in validation infrastructure.
Technologies
Python, C/C++, FPGA, Emulation platforms, Bare metal, OS environments
Responsibilities
Develop and execute comprehensive validation strategies for power states, DVFS, idle and active power management, and thermal management. Drive root-cause analysis of complex silicon, firmware, hardware, and software issues impacting power and stability. Define validation requirements, test plans, methodologies, automation frameworks, and debug tools. Lead silicon bring-up, feature characterization, and workload-based validation activities. Analyze power, performance, and thermal telemetry to identify bottlenecks and optimize platform efficiency. Influence pre-silicon verification strategies using post-silicon learnings. Provide technical leadership and mentoring in Power Management architecture and debug methodologies.
Seniority
Senior, hands-on IC with leadership responsibilities
