Senior SoC HW (Analog/Functional) Validation Engineer
Core
Senior IC validation engineer responsible for post-silicon validation of analog/functional IO interfaces (PLL, Serdes, high-speed interconnects) and silicon debug tool development.
Role type
Senior IC analog/functional validation engineer
Builds
Custom SoC designs for high-performance computing
Domain
Semiconductor hardware design and validation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Post-silicon validation, analog circuit validation, high-speed IO interface expertise (PCI, CXL), silicon debug, test plan development, validation strategy, hardware/software co-design, debug board development, failure triage, pre-silicon verification planning
Preferred skills
SoC power delivery analysis, Python/C++ scripting, FPGA/emulation platform experience, system-level software/firmware understanding, board-level schematic interpretation, on-chip debug (JTAG, trace), test equipment operation (oscilloscopes, protocol analyzers)
Technologies
Python, C/C++, JTAG, FPGA, emulation platforms, oscilloscopes, protocol analyzers, bit error rate testers
Responsibilities
Define and implement silicon debug tools, develop validation strategies and test environments, execute post-silicon test content and triage failures, provide technical mentorship to engineering teams, collaborate with partners to improve validation methodologies, support pre-silicon verification plans
Seniority
Senior, hands-on IC
