FPGA Digital Design Engineer (6+ month Contract)
Core
Design and implement FPGA code for DSP algorithms and embedded systems on Kepler satellites to enable real-time space communications.
Role type
FPGA Digital Design Engineer
Builds
Custom IP for satellite digital payloads and communications/network architecture
Domain
Aerospace / Satellite Communications
Required skills
FPGA/RTL design, Verilog/SystemVerilog/VHDL, Xilinx Zynq/UltraScale, timing closure, Python/Tcl scripting, HDL simulation
Preferred skills
Coherent digital demodulation (BPSK/QPSK/QAM), memory-mapped interfaces (AXI/Wishbone), high-speed transceivers (JESD204B/PCIe), PCB design, RF electronics
Technologies
Vivado, Quartus, ModelSim, Questa Sim, Riviera-Pro, Xilinx Versal, RFSoC
Responsibilities
Develop custom IP for new satellite features, iterate on DSP/interface designs, integrate IP core vendor functionality, collaborate on communications architecture, participate in spacecraft conceptual design
Seniority
Mid-Senior, hands-on IC
