SDE, MLA hardware/software co-design, Annapurna Labs Machine Learning Acceleration
Core
Driving pre-silicon hardware/software co-development for custom machine learning chips (Trainium) to build new silicon functionality and verify SoC end-to-end performance.
Role type
Senior IC embedded software engineer (hardware/software co-design)
Builds
Pre-silicon silicon functionality and SoC subsystems for machine learning chips
Domain
Semiconductor hardware design and embedded software
Deliverable
production ML models
Required skills
bare-metal software development, system development, chip design, embedded software, SoC verification, subsystem performance analysis
Preferred skills
full software development life cycle, coding standards, code reviews, source control management, build processes, testing, operations
Technologies
bare-metal environments, SoC emulation tools
Responsibilities
Write bare-metal software to verify end-to-end SoC functionality, collaborate with architecture and design teams to build new silicon features, analyze subsystem functionality and performance
Seniority
Senior, hands-on IC
