Sr. SDE, MLA hardware/software co-design, Annapurna Labs Machine Learning Acceleration
Core
Pre-silicon hardware/software co-development and verification for next-generation AI chips (Trainium) and machine learning accelerators.
Role type
Senior IC SDE (Hardware/Software Co-design)
Builds
Custom machine learning chips and SoCs for AWS Trainium instances
Domain
Semiconductor hardware design, embedded systems, wireless communications, and machine learning acceleration
Deliverable
production ML models | infrastructure
Required skills
ASIC implementation, digital design, full-custom analog/RF layout, wireless communications systems, automation frameworks, verification, UVM, C, System C, emulation, Python, Embedded C, low power design, modem algorithms, link/system level simulation, bare-metal environment development
Preferred skills
RTL coding and debug, performance/power/area analysis, modern ASIC/FPGA design tools, SOC bring-up, post-silicon validation
Technologies
UVM, MATLAB, Python, C++, Pearl, Git, CI/CD
Responsibilities
Write bare-metal software and ML workloads to verify end-to-end functionality and performance of SoCs; work with architecture, design, and emulation teams to build and test next-generation AI chips; develop methodology and scripts for physical synthesis; develop link and system level simulators; develop test setup automation; develop PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors
Seniority
Senior, hands-on IC
