Yield Enhancement Engineer, Texas Institute for Electronics
Core
Drive yield improvement, defect reduction, process optimization, and new technology development for advanced packaging technologies.
Role type
Yield Enhancement Engineer
Builds
Advanced packaging manufacturing processes and products
Domain
Semiconductor manufacturing / Advanced packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Statistical data analysis (JMP, Minitab, Python, Excel), SPC, DOE, Cp/Cpk, yield analysis, defect reduction methodologies, electrical test data analysis, inline metrology correlation, root cause analysis, process integration studies, failure analysis
Preferred skills
Advanced packaging technologies (hybrid bonding, TSV, Cu damascene, wafer-level packaging), reliability failure mechanisms, automation/data visualization tools, AI/ML-based yield analytics
Technologies
JMP, Minitab, Python, Excel
Responsibilities
Analyze electrical, inline, defectivity, and reliability data to identify yield loss mechanisms; Develop and execute yield improvement plans for NPI and high-volume manufacturing; Perform process integration studies across lithography, etch, deposition, CMP, plating, cleaning, and metrology; Correlate process parameters with yield, reliability, and device performance metrics; Drive root cause analysis using DOE, SPC, Pareto analysis, FMEA, and statistical methodologies; Support technology transfer from development to manufacturing; Monitor excursion trends and establish preventive actions; Define process control strategies, specifications, and yield monitoring methodologies; Participate in failure analysis reviews and develop containment/corrective action plans; Support customer qualification activities and technical discussions; Generate technical reports, presentations, and documentation
Seniority
Mid-level IC
