Principal RFIC Design Engineer - TeraWave
Core
Design and develop RFICs and mixed-signal ASICs for a multi-orbit satellite communications network delivering up to 6 Tbps symmetrical data speeds.
Role type
Principal RFIC Design Engineer (Silicon Systems)
Builds
Optically interconnected satellites in LEO and MEO for enterprise-grade global connectivity
Domain
Space-based communications, RFIC, Mixed-Signal ASIC
Deliverable
production ML models | product features
Required skills
RFIC design, mixed-signal ASIC design, Cadence Virtuoso, Spectre RF, analog modeling for verification, test plan execution, analog impairment tradeoffs, Linux development environment, tape-out experience
Preferred skills
Full RF CMOS ASIC lifecycle management, Software-Defined Radio architectures, ADC/DAC/DSP experience, DSP and communications systems knowledge (OFDM, QPSK, QAM), mentoring junior engineers
Technologies
Cadence Virtuoso, Spectre RF, Linux
Responsibilities
Design and develop RFICs and mixed-signal ASICs; Implement designs using Cadence Virtuoso and Spectre RF; Develop analog models for verification; Create and execute test plans for pre and post silicon processes; Conduct noise, linearity, power, mismatch, and other analog impairment tradeoffs; Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering; Support lab integration and troubleshooting activities; Resolve design and layout issues regarding interface timing and congestion; Adopt AI-based methodologies throughout the design cycle
Seniority
Principal, hands-on IC design with mentorship
