Senior FPGA / RTL Design Engineer - Signal Processing
Core
Design and implement signal processing algorithms for MIMO wireless networking products using FPGA technology.
Role type
Senior FPGA Design Engineer (Signal Processing)
Builds
MIMO wireless networking radios and advanced communication systems for defense and public safety
Domain
Defense, Law Enforcement, Public Safety; Wireless Communications; FPGA/RTL Design
Deliverable
production ML models | product features
Required skills
FPGA design, RTL coding, fixed-point arithmetic, digital signal processing, multi-clock-domain design, Xilinx Vivado, hardware verification
Preferred skills
MATLAB, communication systems on ASIC
Technologies
Xilinx FPGAs, SoCs, Vivado IDE, logic analyzers
Responsibilities
Digital design architecting for wireless communication projects, Fixed point design of signal processing blocks, RTL coding, simulation, and test bench development, FPGA synthesis and timing closure, Hardware verification and troubleshooting, Provide support to RF and Software Engineering teams
Seniority
Senior, hands-on IC