Senior FPGA / RTL Design Engineer - Signal Processing
Core
Senior FPGA Design Engineer implementing novel signal processing algorithms for MIMO wireless networking products and supporting advanced wireless systems R&D.
Role type
Senior IC FPGA/RTL Design Engineer (Signal Processing)
Builds
MIMO wireless networking radios and advanced wireless communication systems
Domain
Defense, law enforcement, public safety; Wireless communications, MANET, MIMO
Deliverable
production ML models | product features
Required skills
FPGA design, RTL coding, simulation, test bench development, FPGA synthesis, timing closure, hardware verification, fixed-point binary arithmetic, digital signal processing, multi-clock-domain design, high-utilization FPGA design, Xilinx FPGAs, SoCs, Vivado IDE
Preferred skills
MATLAB, communication systems on FPGA or ASIC designs
Responsibilities
Digital design architecting for wireless communication projects, Fixed point design of signal processing blocks, RTL coding and test bench development, FPGA synthesis and timing closure, Hardware verification and troubleshooting, Provide support to RF and Software Engineering teams
Seniority
Senior, hands-on IC
