Intern: Application Engineering - Digital Verification & Simulation/VIP
Core
Intern role providing technical support and guidance on RTL-level digital verification and simulation methodologies to customers using Cadence tools.
Role type
Application Engineering Intern (Digital Verification & Simulation)
Builds
Customer enablement for RTL verification IP solutions and supporting technologies
Domain
Semiconductor design automation / Electronic design automation (EDA)
Deliverable
client delivery
Required skills
Problem-solving, Scripting (TCL, Python), Root cause analysis, Test case development, Documentation authoring
Preferred skills
RTL (Verilog/VHDL) exposure
Technologies
Xcelium, Palladium, Protium, Jasper, VIPs, Perspec, TCL, Python
Responsibilities
Provide technical support to customers and field personnel on RTL verification solutions; Conduct root cause analysis and resolve customer technical issues; Develop and run test cases to verify problems and deliver R&D fixes; Collaborate with R&D on issues using established protocols; Author application notes and provide feedback on documentation; Use scripting languages for flow development and automation.
Seniority
Intern, mentored by experienced colleagues