SSG Design Engineering Intern (Fall 2026)
Core
Design Engineering Intern working on Digital Design and Design Verification tasks for the Janus NoC IP product.
Role type
Design Engineering Intern
Builds
Digital IP solutions for Network on Chip (NoC) used in System on Chips (SoCs) and Chiplets
Domain
Semiconductor design IP, System on Chips (SoCs), Network on Chip (NoC)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital Design fundamentals, Design Verification fundamentals, System Verilog, UVM, SVA, Tcl scripting, Perl scripting, shell scripting, EDA tools (synthesis, place & route)
Preferred skills
Exposure to design automation tools
Responsibilities
Implement RTL logic for micro-architecture, simulate and debug RTL, run synthesis and place & route, develop test plans, write functional tests and verification monitors, debug verification failures, analyze coverage information, script verification flows
Seniority
Intern
